
module sadrls0c4l2p16x30m2b1w0c1p0d0t0s2z0rw00 (
input [3:0] ADRA,
input [29:0] DA,
input WEA,
input MEA,
input CLKA,
input TEST1A,
input RMEA,
input [3:0]RMA,
input [3:0]ADRB,
input MEB,
input CLKB,
input TEST1B,
input RMEB,
input [3:0] RMB,
input [29:0] QB	
);

endmodule


module sasrls0c4LOW1p512x20m4b2w1c1p0d0t0s2z0rw00 (
input  [8:0]ADR,
input  [19:0]D,
input  [19:0]WEM,
input  WE,
input  ME,
input  CLK,
input  TEST1,
input  TEST_RNM,
input  RME,
input  [3:0]RM,
input  BC1,
input  BC2,
input  [19:0]Q
);

endmodule


module sasrls0c4LOW1p512x106m2b1w1c1p0d0t0s2z0rw00 (
input  [8:0]ADR,
input  [105:0]D,
input  [105:0]WEM,
input  WE,
input  ME,
input  CLK,
input  TEST1,
input  TEST_RNM,
input  RME,
input  [3:0]RM,
input  BC1,
input  BC2,
input  [105:0]Q
);

endmodule


module sasrls0c4LOW1p512x4m4b2w1c1p0d0t0s2z0rw00 (
input  [8:0]ADR,
input  [3:0]D,
input  [3:0]WEM,
input  WE,
input  ME,
input  CLK,
input  TEST1,
input  TEST_RNM,
input  RME,
input  [3:0]RM,
input  BC1,
input  BC2,
input  [3:0]Q
);

endmodule


